Semiconductor memory devices are used in a wide variety of contexts. One type of memory is a static random access memory (SRAM). This type of memory is considered static because it will retain its state without need for refresh. A system that utilizes an SRAM will typically have dedicated SRAM memory chips or will include the memory on-chip with other circuitry, e.g., embedded memory. The present invention is applicable in either case.
FIG. 1 is a circuit diagram of one type of SRAM memory cell, namely, a one-transistor SRAM (1T-SRAM). Generally, the memory cell of a 1T-SRAM includes a bit line BL, a word line WL, a capacitor 110, and a transistor 112. The word line WL is connected to the gate of the transistor 112. The source and drain of the transistor 112 is electrically coupled to the capacitor 110 and the bit line BL. The bottom plate of the capacitor 112 is generally electrically coupled to ground.
In operation, the capacitor 110 stores a charge representing a logic “0” or a logic “1.” The capacitor 110 is written to or read from by activating the word line WL, thereby allowing a charge to flow from the capacitor 110 to the bit line BL during a read cycle and allowing a charge to flow from the bit line to the capacitor 110 during a write cycle. During the read cycle, the value read via the bit line BL is generally conducted to a sense amp (not shown) wherein the signal is amplified and conducted to other circuitry (not shown).
FIG. 2 is a cross section of a metal oxide semiconductor (MOS) circuit 200 implementing the circuit illustrated in FIG. 1. The circuit 200 is formed on a substrate 202, which is generally a silicon or glass substrate. The capacitor 110 has a dielectric layer 210 placed between a top electrode 212 and a bottom electrode 214. The dielectric layer 210 is typically silicon dioxide or some other oxide, and the top electrode 212 is typically a conductive metal or a doped polysilicon. The bottom electrode 214 is typically a conductive metal, a doped polysilicon, or doped area of the substrate. The transistor 112 typically has a gate electrode 214 and a gate oxide 216. The transistor 112 has its source and drain coupled to the capacitor 110 and the bitline BL via doped areas 218 of the substrate. A shallow-trench isolation (STI) structure 220 may be used to isolate the memory cell from other circuitry. The memory cell may be constructed as either a p-channel MOS (PMOS) or an n-channel MOS (NMOS) structure.
During fabrication, periphery devices, such as transistors, are also located on the same chip or die as the memory cell discussed above. The top plate 212 of the capacitor 110 is typically formed of a doped polysilicon material and is formed in the same process step as the gates for transistors, which also utilize a doped polysilicon material. Furthermore, the dielectric layer 210 is typically formed in the same process step as the transistor gate oxide in the periphery and core regions.
Fabricating the top plate 212 and the dielectric layer 210 of the capacitor 110 in the same process step as the transistor gate oxide 216 and gate electrode 214, however, requires that the doped concentration and thickness of the top plate 212 and the transistor gate electrode 214 be substantially equivalent. Utilizing the same dopant concentration for electrodes 212 and 214 and the same thickness for dielectric layers 210 and 216 may cause capacitance leakage and/or low capacitance. In other words, increasing the oxide thickness to reduce capacitor leakage impacts the logic gate oxide performance, and decreasing the oxide thickness to gain higher capacitance also impacts the logic gate oxide performance.
Therefore, there is a need for a method of fabricating memory devices to reduce capacitance leakage or increase capacitance.